The present invention relates to technique for reducing power consumption during standby time of a CMOS semiconductor logic integrated circuit.
In the present invention, standby time of an integrated circuit refers to a time period of a sleeping status or a non-operating status, in which the integrated circuit waits for input or occurrence of a certain predicted signal and shifts to a next predicted operation.
In the case of an electronic in which standby time makes up a large proportion relative to an operating time and a battery is used as a power voltage supply source, it has become a common practice to suspend almost all the operations of the integrated circuit and an operating clock of its surrounding circuit so as to cut the power consumption, thereby maximizing the life expectancy of the battery.
Further, in recent years, longer life expectancy of a battery has become increasingly important as a customers"" criterion for purchasing a portable electronic and a goal of competitive performance.
Power leakage current of a CMOS semiconductor logic integrated circuit is categorized into leakage on a depletion layer for element separation, off leakage on a transistor channel, and leakage between wirings. In a time when a transistor has a minimum gate length of 1 xcexcm or more, off leakage current of a transistor channel is smaller than reverse bias leakage current of the depletion layer, resulting in no problem.
However, at the present time of sub xcexcm and deep sub xcexcm, off leakage current of a transistor channel cannot be negligible as compared with other leakage currents.
This is why power consumption rises with increasing power leakage current during standby time of an MOS semiconductor logic integrated circuit.
In recent years, power consumption is likely to increase because of a larger number of transistors per chip of an integrated circuit, higher performance of an electronic, and the enhanced speed of an operating clock with faster response. Additionally, the demand for an electronic is shifted from a stationary electronic provided for each family to a portable electronic for each person, so that it is necessary to increase the life expectancy of a battery installed into an electronic. Furthermore, because of the need for a smaller and a thinner model, an electronic is downsized such that a permissible loss heat packaging capacity of an integrated circuit package is further limited and power consumption of that circuit is largely reduced under operation.
The most effective means for solving the above problem is to lower operating source voltage, which can reduce power consumption in inverse proportion nearly to the second power.
Therefore, in order to realize a low source voltage and a high-speed integrated circuit, the designer has set a gate threshold voltage of a transistor, which is installed into a semiconductor, at a voltage decreasing proportionally to source voltage, even though a channel-off leakage current is sacrificed to some extent.
However, a channel-off leakage current of the transistor is determined by semiconductor diffusion parameters such as a diffusion coefficient of the channel, a thickness of a gate oxide film, and a gate threshold voltage. Thus, under present circumstances, after the completion of the integrated circuit, the designer who installs the integrated circuit on the market into the electronic does not have any effective means for reducing power consumption increased by leakage current.
For this reason, the following measure (1-1) or (1-2) has been conventionally taken as a means for reducing power consumption during standby time.
(1-1) During standby time, memory information is held, which is necessary for continuing the operation of an integrated circuit, and a minimum source voltage is applied during standby time so as to immediately make a shift to the following operating status without formatting or resetting.
(1-2) In order to reduce a channel-off leakage current of the transistor, a high gate threshold voltage is applied during standby time to deepen a back gate bias voltage.
However, the use of the above means causes the following disadvantage (1-3) or (1-4).
(1-3) In case of (1-1), with a low source voltage applied during standby time, it is not possible to attain a design target value of power consumption during standby time because of quite too large a number of transistors provided in the integrated circuit.
(1-4) In case of (1-2), during standby time, a gate threshold voltage is increased higher than that of the operating status. Hence, in a CMOS semiconductor integrated circuit, a source voltage supply circuit is installed to set a back gate bias voltage higher than a source voltage on a P-channel transistor and lower than a ground voltage on an N-channel transistor, thereby increasing the cost.
Moreover, in case of (1-4), a back gate bias potential of each transistor is not direct-coupled to a source output with low impedance but is coupled to a high-impedance source output of a built-in source voltage supply circuit, which is less likely to incorporate a large-capacity capacitor for reducing power impedance. Thus, a latch-up withstand voltage is lowered by a parasitic transistor in the integrated circuit.
In order to lower the impedance of the internal source voltage supply circuit, it is necessary to append the source output on an external terminal of the integrated circuit and to externally connect a large-capacity bypass capacitor thereon.
Therefore, (1-3) is disadvantageous because the means is useless for reducing power consumption during standby time. (1-4) is disadvantageous because the cost is increased by adding the source voltage supply means.
In order to reduce power consumption during standby time of the CMOS semiconductor integrated circuit, the most effective means is to interrupt source voltage on a circuit part during standby time, which does not cause any problems in a subsequent resetting.
As for a timing function provided in an electronic, it is necessary to always apply source voltage regardless of standby time or operating time, because ticking is always required.
However, regarding a standby function of a mobile phone, a phone is in a standby status and its operation can be suspended to reduce the consumption of a battery source capacity, except for when the presence of an incoming call to its telephone number is intermittently confirmed at a fixed time interval.
In general, the integrated circuit is configured by the connection of a memory circuit, which always needs to store information for a continuous operation, and combinational logic gates, which do not have to store the information.
In the memory circuit, regarding register elements and memory elements (hereinafter, these elements are referred to as temporary memory elements) in which stored information is erased upon interruption of source voltage, if a means is adopted for preventing stored information from being erased, the object of the present invention can be attained even in the case where source voltage is interrupted on a logic gate element of the combinational logic gates, a buffer element, a permanent memory element for holding stored information under the interruption of source voltage, an analog function element, or other elements (hereinafter, these elements are referred to as elements other than the temporary memory elements).
Namely, in this case, in order to reduce power consumption during standby time, a proposal is made that a source voltage be applied only to the following (2-1) and (2-2) as the fewest elements having to receive source voltage in the integrated circuit during standby time and source voltage supply be totally suspended on the other elements except the temporary memory elements.
(2-1) All the temporary memory elements.
(2-2) Elements other than the temporary memory elements of the integrated circuit that make electrical connection with external devices of the integrated circuit and need to maintain electrical exchange of information or a controlling status and a controlled status with the external devices.
In the case where the transistors constituting all the integrated circuits including the above (2-1) and (2-2) are equal in size, namely, if the transistors are equal in channel-off leakage current, estimated standby power consumption can be reduced to a ratio of the number of transistors for elements other than the temporary memory elements to the number of transistors per chip.
However, when a source voltage is interrupted on the elements other than the temporary memory elements in the CMOS semiconductor integrated circuit, on which the temporary memory elements and the other elements are combined, the following problems (2-3) and (2-4) occur. Thus, it is not possible to hold stored information for returning from a standby status to an operating status just before the standby status. Further, power consumption during standby time cannot be reduced. Consequently, it has not been conventionally possible to totally interrupt source voltage applied to the elements other than the temporary memory elements during standby time.
(2-3) Regarding the elements other than the temporary memory elements that are connected to input terminals of the temporary memory elements, output voltage becomes unstable, so that information stored in the temporary memory elements is corrupted by unexpected setting, resetting, clocking, or trigger input of writing.
(2-4) Source voltage is interrupted on the elements other than the temporary memory elements that are connected to output terminals of the temporary memory elements, so that unexpected power leakage current is applied from source terminals of the temporary memory elements to the elements other than the temporary memory elements via the output terminals of the temporary memory elements, resulting in larger power consumption.
Therefore, in order to keep applying source voltage only to the temporary memory elements while maintaining information stored in the temporary memory elements just before a standby status, to interrupt source voltage on the elements other than the temporary memory elements, and to resume the application of source voltage to the elements other than the temporary memory elements so as to resume the operation in a state just before the standby status, the present invention aims to attain the following (2-5) and (2-6) regarding all the inputs, outputs, and I/O terminals of the temporary memory elements that connect the temporary memory elements and other elements, during the interruption of source voltage on the elements other than the temporary memory elements.
(2-5) A means for preventing the passage of the unstable voltage, which is described in the above(2-3), from the elements other than the temporary memory elements.
(2-6) A means for preventing the passage of the power leakage current, which is described in the above (2-4), to the elements other than the temporary memory elements.
A semiconductor register element described in claim 1 of the present invention is characterized in that in a circuit network of a CMOS semiconductor integrated circuit, a source voltage supply system is divided into a first source wiring and a second source wiring. The first source wiring feeds temporary memory element groups, which store information only when source voltage is applied, and the second source wiring feeds element groups other than the temporary memory element groups. The element groups other than the temporary memory element groups are each configured by a non-memory element group acting as combinational logic or a buffer, a permanent memory group for holding stored information even when source voltage is interrupted, an analog function element group, or other groups. Output logic is held and the passage of unstable logic is prevented from the element groups other than the temporary memory element groups that are connected to input terminals of the temporary memory elements in the temporary memory element groups. Thus, even when source voltage is interrupted on the element groups other than the temporary memory element groups that are connected to the input terminals of the temporary memory elements in the temporary memory element groups, the stored information of the temporary memory elements can be held without corruption in a state just before source voltage is interrupted on the elements other than the temporary memory element groups. Further, after resuming the supply of source voltage to the elements other than the temporary memory element groups, it is possible to resume the operation of the integrated circuit in a state just before the source voltage is interrupted.
A semiconductor register element described in claim 2 of the present invention is characterized by the following configuration in claim 1. Source voltage is interrupted on the elements other than the temporary memory element groups, the elements being connected to output terminals of the temporary memory elements. Thus, power leakage current can be prevented from passing through the elements other than the temporary memory element groups via source voltage supply terminals and the output terminals of the temporary memory elements.
A semiconductor register element described in claim 3 is characterized by the following configuration in claim 1. When a source voltage supply system is divided for the temporary memory element groups and the element groups other than the temporary memory element groups, the source voltage supply system is divided for the element groups other than the temporary memory element groups where the external devices connected to the integrated circuit need to electrically hold information exchange or a controlling and controlled status with the integrated circuit via the elements other than the temporary memory element groups even when source voltage of the element groups is interrupted. And the division is also made for the element groups other than the memory element groups where the external devices do not have to hold the information exchange or the controlling and controlled status.
A register element described in claim 4 of the present invention is characterized by the following configuration in claim 1. Under control of the temporary memory element groups, stored information of the temporary memory elements is held in a state just before source voltage is interrupted on the elements other than the temporary memory elements, and even though source voltage is interrupted on the elements other than the temporary memory elements that are connected to the input terminals of the temporary memory elements, the operation of the integrated circuit can be resumed in a state just before source voltage is interrupted, after the supply of source voltage is resumed to the element groups other than the temporary memory element groups.
A semiconductor register element described in claim 5 of the present invention is characterized by the following configuration in claim 1. Under control of the external devices connected to the external terminals of the integrated circuit, stored information of the temporary memory elements is held in a state just before source voltage is interrupted on the elements other than the temporary memory elements, and even though source voltage is interrupted on the elements other than the temporary memory elements that are connected to the input terminals of the temporary memory elements, the operation of the integrated circuit can be resumed in a state just before source voltage is interrupted, after the supply of source voltage is resumed to the element groups other than the temporary memory element groups.
A semiconductor register element described in claim 6 is characterized by the following configuration in claim 1. Under control of the temporary memory element groups, source voltage is interrupted on the elements other than the temporary memory elements that are connected to the output terminals of the temporary memory elements, so that power leakage current can be prevented from passing through the elements other than the temporary memory element groups via source voltage supply terminals and the output terminals of the temporary memory elements.
A semiconductor register element described in claim 7 is characterized by the following configuration in claim 3. Under control of the external devices connected to the external terminals of the integrated circuit source voltage is interrupted on the elements other than the temporary memory elements that are connected to the output terminals of the temporary memory elements, so that power leakage current can be prevented from passing through the elements other than the temporary memory element groups via source voltage supply terminals and the output terminals of the temporary memory elements.
A semiconductor register element described in claim 8 of the present invention, in claim 1 or 2, is characterized by performing the steps of holding output logic transmitted from the elements other than the temporary memory elements just before source voltage is interrupted on the elements other than the temporary memory elements that are connected to the input terminals of the temporary memory elements, preventing the passage of unstable logic just after source voltage is interrupted on the elements other than the temporary memory elements, preventing power leakage current appearing on the elements other than the temporary memory elements that are connected to the output terminals of the temporary memory elements, and then interrupting source voltage on the elements other than the temporary memory elements; and the steps of eliminating prevention of power leakage current appearing on the elements other than the temporary memory elements that are connected to the output terminals of the temporary memory elements just after the supply of source voltage is resumed to the elements other than the temporary memory elements, eliminating the holding of the output logic and prevention of unstable logic from the elements other than the temporary memory elements that are connected to the input terminals of the temporary memory elements, and then resuming the operation of the integrated circuit.
As a means for solving the foregoing problem, the following configuration is provided, which realizes the step of making shift to a standby status and returning to an operating status.
Namely, upon shifting from an operating status to a standby status, the following (3-1) to (3-3) are carried out in order.
(3-1) First, regarding all the input terminals such as setting, resetting, clocking, and data writing of the temporary memory elements connected to the output terminals of the elements other than the temporary memory elements, necessary input logic is held and passage of an unstable logic value is prevented from the elements other than the temporary memory elements after source voltage is interrupted.
(3-2) And then, the passage of current is interrupted from all the output terminals such as reading data of the temporary memory elements to the elements other than the temporary memory elements.
(3-3) Finally, the passage of source voltage is interrupted to the elements other than the temporary memory elements except for the foregoing (2-2).
Meanwhile, upon returning from a standby status to an operating status, the following (3-4) to (3-6) are carried out.
(3-4) First, the supply of source voltage is resumed on the interrupted elements other than the temporary memory elements.
(3-5) And then, the supply of voltage is resumed from all the output terminals such as reading data of the temporary memory elements to the elements other than the temporary memory elements.
(3-6) Finally, the supply of a signal is resumed from the output terminals of the elements other than the temporary memory elements to all the input terminals such as setting, resetting, clocking, and writing of the temporary memory elements. Since the above means are carried out in order, the foregoing (2-5) and (2-6) can be completed.
It is particularly significant to perform the steps from (3-1) to (3-2) and the steps from (3-4) to (3-5) in order to prevent stored information of the temporary memory elements from being corrupted. The corruption is caused by unstable input logic transmitted from the elements other than the temporary memory elements to the temporary elements.
According to the above configuration, since the configuration of a CMOS semiconductor integrated circuit has been increasingly fine, in the case of a mobile phone where a battery is necessary as a power voltage supply source, the semiconductor register elements of the present invention can achieve great effect by reducing standby power consumption with an increasing ratio of standby time serving as a receiving status to operating time serving as a conversation status.